With the continuing increase in the architecture complexity and integration density of semiconductor circuits, the impact of particulate defects is a significant control factor in wafer probe yield. The potential of the particulates to effectively negate or "kill"a circuit depends upon their location on the wafer (i.e. coincidence with a circuit element) and also upon minimum feature size (MFS), namely, the smallest geometry of one or more of the process mask levels. In the manufacture of CMOS devices, for example, MFS is usually determined by gate length, contact aperture size or metal width/spacing. Yield analysis of a number of bulk CMOS processes having a minimum feature size ranging from 0.5 to 3 microns has suggested that only particles of a size greater than one-fifth of the minimum feature size are potential "killer"particles for that process. Thus, for a three micron MFS fabrication process only particles greater than 0.5.mu. are potentially fatal.
Processing complexity, which is a natural consequence of integration density and circuit design complexity, depends upon the number of critical steps which, in turn, are related to the number of masking operations. Thus, increases in processing complexity and integration density, for a constant minimum feature size, have been accompanied by a significant increase in circuit killer particle density. Namely, as circuit density is increased (other than by decreasing MFS), the likelihood of an existing particulate defect killing a circuit (of constant area) increases.
Historically, efforts to decrease the density of killer particles have principally involved increased attention to sources of the particulates, i.e. cleanliness. The progression rate at which the introduction of particles into the manufacturing process can be prefiltered out, however, is relatively sluggish; at the current progression rate of 25% per year it is estimated that it would take five years to increase wafer probe yield from 10% to 30% under constant MFS conditions, which effectively corresponds to being able to avoid one defect per circuit. It would take twelve years, at normal progression, to equal the yield improvement of avoiding two defects per circuit.